1. Field of the Invention
The present invention relates to a display device such as an active matrix type one.
2. Description of Related Art
A conventional driving circuit integrated-type active matrix liquid crystal display will be explained.
As a polysilicon TFT (thin film transistor) formed on an insulating substrate, an expensive quartz substrate was required for a high temperature process, so it was applied to a small display panel with high-value added. Then, a technique for forming a precursor film by low pressure (LP) CVD (chemical vapor deposition), plasma (P) CVD, or sputtering, which is annealed with a laser to thereby polycrystallize, that is, a technique for forming a polysilicon TFT at a low temperature capable of using a glass substrate or the like has been developed. At the same time, an oxide film forming technique, a fine processing technique, a circuit design technique and the like have been developed. Consequently, there have been produced polysilicon TFT display panels for mobile phones, portable information devices, and note PCs in which surrounding circuits of a display panel are integrated on the same substrate.
As shown in FIG. 19A, a conventional liquid crystal display device (see publication of Japanese Patent Laid-open No. 2004-46054, pp. 31 to 32 and FIGS. 37 and 38 (Patent Document 1)) is so configured as to include: an active matrix display area 110 on which wirings are arranged in a matrix and pixels are aligned in M lines and N rows; a scan circuit (scan line (gate line) driving circuit) 109 in a line direction; a scan circuit (data line driving circuit) 3504 in a row direction; an analog switch 3505; and a level shifter 3503, which are formed integrally with a polysilicon TFT on a display device substrate 101. A controller 113, a memory 111, a digital/analog conversion circuit (DAC circuit) 3502, a scan circuit/data resistor 3501, for example, are integrated circuit chips (IC chips) formed on a monocrystalline silicon wafer, which are mounted outside the area of the display device substrate 101. The analog switch 3505 has the number of outputs same as the number N of data lines in the row direction of the active matrix display area 110.
Further, some conventional driving circuit integrated-type liquid crystal display devices consisting of polysilicon TFT, are so formed that more complicated circuits such as DAC circuits are integrated. A liquid crystal display device of the DAC circuit integrated type includes, as shown in FIG. 19B, an active matrix display area 110 on which wirings are arranged in a matrix and pixels are aligned in M lines and N rows, a scan circuit 109 in a line direction, and a scan circuit 3506 in a row direction, same as those of the device shown in FIG. 19A in which DAC circuits are not integrated, and further includes circuits such as a data register 3507, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a level shifter/timing buffer 108 are formed integrally on the display device substrate 101.
In a liquid crystal display device shown in FIG. 19B, a controller IC mounted outside the area of the display device substrate 101 can consist solely of low voltage circuits and elements such as the memory 111, the output buffer 112, the controller 13, without a DAC circuit using high voltage. As a result, the IC can be produced without using a process for high voltage which is required for generating voltage signals for writing into liquid crystal. Therefore, the price can be suppressed lower than that of an IC incorporating the DAC. The liquid crystal display device shown in FIG. 19B has such features as thin and light, so the liquid crystal display device shown in FIG. 19B is mounted on a portable type information processor by using the features.
The liquid crystal display devices shown in FIGS. 19A and 19B are examples of a typical CMOS (complementary metal-oxide semiconductor) configuration. With the CMOS configuration, a shift resistor circuit constituting scan circuits such as a scan circuit 109 in a line direction or a scan circuit 3506 in a low direction can be realized with an inverter circuit and a statistic circuit using a clocked inverter circuit.
Not only a TFT circuit of the CMOS configuration, there has been also proposed a driving circuit integrated-type display device consisting solely of NMOS or PMOS, that is, a so-called single channel TFT. A single channel TFT circuit can be produced through saved processes comparing with a TFT circuit of CMOS configuration, so the cost is expected to be low. A shift register consisting of the single-channel TFT described above is disclosed in publication of Japanese Patent No. 2836642, p. 4, FIGS. 1 to 4 (Patent Document 2).
As shown in FIG. 20A, the liquid crystal display device includes a plurality of stages 11, which are substantially same, in the shift register 10. Each of the stage 11 has an input terminal 12 and an output terminal 13. The stages 11 are cascade-connected. That is, the output terminal 13 of each stage 11 is connected with the input terminal 12 of the next stage, and each stage 11 has two clock input terminals 14 and 15. A clock generator 22 generates three clock signals C1, C2 and C3 in which phases thereof are shifted to each other. Pairs of clock signals, each pair of which has a different combination, are inputted into clock terminals 14 and 15 of each stage 11, and each stage 11 receives a pair of clock signals different from pairs of clock signals received by the stages of the both adjacent sides. Relationships between the clock pulses C1, C2 and C3 and four output pulses are shown in FIG. 21A.
Each stage shown in FIG. 20A is configured by combining a plurality of TFT 16 to 21, as shown in FIG. 20B.
In the stages 11 shown in FIGS. 20A and 20B, the level of a node P2 at a time T0 is high as shown in FIG. 21B, and the TFT 17 is ON, and an output terminal 13 of the stage 11 is biased at a low voltage VSS.
When an input pulse is inputted into the input terminal 12 of the stage 11 and the clock pulse C3 is supplied to a clock terminal 15, TFT 18, 20 and 21 at the stage 11 are turned on simultaneously. Therefore, the voltage value of the node P1 of the stage 11 starts to be positive toward a voltage value equal to VDD-Vt. Here, Vt is a threshold voltage of the TFT 18. Thereby, the TFT 16 of the stage 11 is biased. At the same time, since the TFT 21 at the stage 11 is in an ON state, the node P2 becomes a Lo level.
When the node P2 at the stage 11 becomes a Lo level, the TFT 17 of the stage 11 is in an OFF state but the clock pulse C1 of the stage 11 is in a Lo level, so the output terminal 13 of the stage 11 remains at the Lo level. When the clock pulse C1 of a Hi level is inputted into the clock terminal 14 of the stage 11, the TFT 16 of the stage 11 has been pre-charged to a Hi level, and further, the node P1 of the stage 11 is pressurized due to a fixed stray capacitance of gate/drain. Thereby, the output terminal 13 of the stage 11 can follow the clock signal C1. Therefore, selection lines (gate lines) of the display device are charged to a desired voltage with the output pulses, and further, input pulse of Hi level is supplied to the subsequent stage.
Next, reverse driving of a counter electrode in a liquid crystal display device will be explained.
A display device substrate 101 shown in FIG. 19 is combined with a counter substrate, and an electric optical element is interposed between the display device substrate 101 and a counter substrate to thereby constitute the display area 110 of the liquid crystal display device.
As shown in FIG. 22A, pixels formed on the display area 110 includes a TFT 1800 for performing switching action, a data line 1011, a gate line 1010, a storage stray capacitance 1802, a common line 1801, an electric optical element (liquid crystal) 1004, and a counter electrode 1002. A switch TFT 1800 shown in FIG. 22A consists of a NMOS TFT.
As shown in FIG. 22A, voltage applied to the gate line 1010 of the display area 110, that is, voltage applied to respective gate lines G1, G2, . . . Gn−1 and Gn becomes Hi level sequentially with a time lag. When the voltage of the gate line 1010 becomes Hi voltage, the switch TFT 1800 is in an ON state, and the data line 1011 and the node A of the storage stray capacitance 1802 are in a conductive state, whereby the voltage of the data line 1011 is applied to the node A. That is, data is written. At this time, potential differences Vcom between the common line 1801 and the counter electrode 1002 are equal in all gate lines, as shown in FIG. 22B. Here, a voltage difference between the node A and the counter electrode 1002 is a voltage applied to the liquid crystal 1004. Since the transmittance of the liquid crystal 1004 is different depending on the voltage, the liquid crystal 1004 serves as a display element by controlling the voltage. Further, as shown in FIG. 22B, the level of the potential difference Vcom reverses to Hi level or to Lo level by each neighboring gate line 1010, and further reverses by frame. When the level of the voltage difference is caused to be reversed as described above, there is a merit that voltage amplitude of the data line 1011 is smaller comparing with the case of driving the level of the voltage difference Vcom constant.
Although the configuration of a TFT substrate has been described in the explanation above, a driving circuit is required for driving pixels of the TFT substrate. Therefore, in order to incorporate a driving circuit into the TFT substrate without interfering the function of the TFT substrate, positioning relationship with the TFT substrate becomes a problem.
In a liquid crystal display device, a TFT substrate and a counter substrate are arranged in parallel facing each other, and liquid crystal is filled between the both substrates. Therefore, in order to fill in the liquid crystal between the both substrates, a gap between the TFT substrate and the counter substrate in the surrounding part thereof should be sealed.
FIG. 23A shows an example of positional relationship between the TFT substrate and the driving circuit (see publication of Japanese Patent Application Laid-open No. 3208909, p. 4, FIG. 3(b) (Patent Document 3)). In FIG. 23A, the reference numeral 301 indicates an element substrate (TFT substrate), 302 indicates a counter substrate, 303 indicates a seal area (seal), 304 indicates a driver circuit (driving circuit), 311 indicates a counter electrode, 312 indicates an orientation film, 313 indicates a pixel driving transistor, 314 indicates a pixel electrode, 315 indicates a contact hole with a pixel electrode, 317 indicates a wiring, 319 indicates a transparent organic insulating film, and 321 indicates a gap agent.
In Patent Document 3, the driver circuit 304 is formed on the element substrate 301 at a position inside the seal area 3030 for sealing the gap between the element substrate 301 and the counter substrate 302.
FIG. 23B shows another example (publication of Japanese Patent No. 2893433, p. 3, FIG. 2 (Patent Document 4)). In FIG. 23B, the reference numerals 17 and 18 indicate glass substrates, 19 indicates a pixel electrode, 20 indicates a thin film transistor, 21 indicates a gate line driving circuit (driver circuit), 22 indicates a drain line driving circuit (driver circuit), 23 and 25 indicate orientation films, 26 indicates a seal member, 28 indicates liquid crystal, and G1 indicates a gate line.
In FIG. 23B, the gate line driving circuit 21 is formed near the seal member 26, and a part of which is covered with the seal member 26, and the remaining part is formed so as to be protruded inward from the seal member 26, that is, to the liquid crystal 28 side.
FIG. 23C shows another example (publication of Japanese Patent No. 3413230, p. 4, FIG. 2(b) (Patent Document 5)). In FIG. 23C, the reference numeral 201 indicates an element substrate, 203 indicates a driver circuit, 206 indicates a seal, 207 indicates a counter substrate, 209 indicates liquid crystal, and 210 indicates a pixel electrode.
In FIG. 23C, the driver circuit 203 is formed within the width area of the seal 206.
FIG. 23D shows another example (publication of Japanese Patent No. 3410754, p. 3, FIG. 2, (Patent Document 6)). In FIG. 23D, the reference numeral 101 indicates a glass substrate (TFT substrate), 102 indicates a pixel TFT, 103 indicates a driver, 106 indicates a pixel electrode, 107 indicates a counter substrate, 108 indicates an adhesive, and 109 indicates a counter electrode.
In FIG. 23D, the adhesive 108 corresponds to a seal for sealing the gap between the glass substrate 101 and the counter substrate 107, and the driver 102 is formed outside the adhesive 108.
Next, the structure of the counter electrode of the counter substrate and the contact structure will be explained by using FIGS. 24A and 24B.
As shown in FIGS. 24A and 24B, an electric optical device is so configured that a liquid crystal layer 50 is interposed between the TFT array substrate 10 and the counter substrate 20, and the gap of the surrounding part between the TFT array substrate 10 and the counter substrate 20 is sealed with the seal 52 provided in the seal area positioned around the pixel display area 10. The seal 52 is made of ultraviolet curing resin or thermal curing resin for adhering the both substrates, and the seal is applied onto the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation or heating. In the seal 52, gap members (spacers) such as glass fibers or glass beads for setting the distance between the both substrates (gap between substrates) to a predetermined value may be scattered, if the electric optical device is a small one performing enlarging display such as one for projector. Alternatively, if the electric optical device is a large one performing same magnification display such as a liquid crystal display and a liquid crystal television, such a gap member may be included in the liquid crystal layer 50.
In parallel with the inside of the seal area where the seal 52 is arranged, a first shielding film 53 defining the frame area of the image display area 10 is provided on the counter substrate 20. In the surrounding area outside the seal area where the seal 52 is disposed, the data line driving circuit 101 and the outside circuit connection terminal 102 are provided along one edge of the TFT array substrate, and the scan line driving circuit 104 is provided along two edges adjacent the one edge. Further, along the remaining one edge of the TFT array substrate 10, there are provided a plurality of wirings 105 for connecting two scan line driving circuits 104 provided on the both sides of the image display area, respectively. Further, in at least one of corner parts of the counter substrate 20, a vertically conductive member 106 for providing electric conductivity between the TFT array substrate 10 and the counter substrate 20 is provided.
In FIG. 24B, on the TFT array substrate 10, an orientation film made of a polyimide material is formed on the pixel electrode 9a after TFT for pixel switching and wirings such as scan lines, data lines and stray capacitance lines are formed. On the counter substrate 20, on the other hand, an orientation film made of a polyimide material is formed on the uppermost layer part (layer positioned the lowermost in FIG. 24B) on which a color filter, a first shielding film 53 and the like are formed besides the counter electrode 21. Each of a pair of orientation films is formed such that a polyimide material is applied in the manufacturing process, and after burnt, orientation processing is performed so as to orient the liquid crystal in the liquid crystal layer 50 in a predetermined direction and to cause the liquid crystal to have a predetermined pre-tilt angle. Further, the liquid crystal layer 50 consists of liquid crystal in which one or several types of nematic liquid crystal are mixed for example, and takes a predetermined orientation state between a pair of orientation films.
In this publicly known example, in a rectangle area shown by the bold line encircling most of the lower edge of the seal 52 in a plan view, the shield layer 8 consisting of a conductor is formed between the seal 52 and the TFT substrate array 10, as shown in FIG. 24B. In particular, the shield layer 80 is interposed between the electric signal lines and the drawing lines thereof and the sampling circuit driving signal lines formed on the TFT array substrate 10, and the counter electrode 21 formed on the counter electrode 20 formed on the counter substrate 20, so as to electrically shield the latter from the former.
Hereinafter, a problem when a dynamic circuit formed of a single-channel TFT as shown in FIG. 20 described above is applied to a display device using an electric optical element will be explained. Generally, in the display device, two substrates are made opposite each other as shown in FIG. 23. That is, a counter substrate exists so as to face a substrate on which the dynamic circuit is formed. The configuration between the substrate on which the dynamic circuit is formed and the counter substrate differs depending on the position where the dynamic circuit is formed.
For example, on the upper face of the driver circuit 304 in FIG. 23A, a liquid crystal member, a gap member 321 and the like exist, and further a counter electrode 311 exist on a face above them. That is, when paying attention to a node at which the driver circuit 304 exists, liquid crystal or liquid crystal and a gap member 321 are interposed between the driver circuit 304 and the counter electrode 311, and a sandwich structure of the driver circuit 304 and the counter electrode forms stray capacitance.
Further, in the gate line driving circuit 21 in FIG. 23B, a part thereof is covered with a seal 26 and a part of the remaining is covered with liquid crystal 28, and common electrodes 24 exist opposite each other. Although it differs depending on whether the gate line driving circuit 21 exists, a sandwich structure of the gate line driving circuit 21 and the common electrode 24 forms stray capacitance.
Further, the driver circuit 203 in FIG. 23C is covered with a seal 206, and the driver circuit 203 and the common electrode 218 exist opposite each other.
The seal 206 shown in FIG. 23C has conductivity, and the seal 206 communicates with an electrode on the counter substrate side not shown. As shown in FIG. 25, the seal 206 communicates with a counter contact 1200 which is an electrode on the TFT substrate side. As obvious from FIG. 25, the counter contact 1200 and the node positioned immediately below thereof having the driver circuit 203 serve as electrodes respectively and form stray capacitance having an interlayer film 207 therebetween.
As described above, the counter electrode 311 shown in FIG. 23A, the common electrode 24 shown in FIG. 23B and the conductive seal 206 shown in FIG. 23C, and the driver circuit 304 shown in FIG. 23A, the gate line driving circuit 21 shown in FIG. 23B and the node of the driver circuit 203 shown in FIG. 23 form stray capacitance by interposing electric optical element and a seal and the like which are dielectrics.
The stray capacitance will be explained based on FIG. 26A. As shown in FIG. 26A, the node N where the driving circuit exists and the counter electrode 1001 form an electrode of the stray capacitance. Liquid crystal, a seal and the like existing between the electrodes serve as dielectrics of the stray capacitance. The distance between the electrodes and dielectric ratio of the dielectrics are parameters of the stray capacitance C shown in FIG. 26A. In FIG. 26A, assuming that the potential of the node N of the driving circuit is Vn, when the node N is in a floating state, Vn becomes one shown in the timing chart showing potential of Vcom and Vn due to the fluctuation of Vcom, as shown in FIG. 26B. That is, with respect to Vcom fluctuating with amplitude from VH to VL, the node N which is a floating node fluctuates from VH′ to VL′.
A problem when the potential of the node in a floating state varies due to fluctuation of Vcom will be explained specifically in accordance with the publicly known example of Patent Document 2. Referring to FIGS. 20B and 21B, in a state where an input becomes the Lo level, the TFT 18 becomes an off-state. At this time, since the node P2 is in an off-state, the TFT 19 is also in an off-state. Therefore, the node P1 is in a floating state, so potential of the node P1 varies in the same way as Vn in FIG. 26B. Since the potential of the node P1 is a voltage applied to the gate of the TFT 16, when the potential of the node P1 is lowered than a design value, the current driving capacity of the TFT 16 is lowered. In contrast, when the potential of the node P1 rises from the design value, voltage more than required is applied to the TFT 16. In the former case, a period for reaching the Hi level of the output 1 increases so as to cause delay in the circuit operation, so operation margin decreases. In the latter case, reliability is lowered due to voltage and current stress of the TFT 16.
In particular, in Patent Document 5, the forming position of the stray capacitance is not a position where the counter substrate and the node of the TFT circuit face each other, but a position where the wiring used as a contact between the seal and the TFT substrate and the node of the TFT circuit face each other. Therefore, the stray capacitance value of the stray capacitance is very large. Therefore, since the fluctuation value becomes large necessarily, the problem becomes prominent.
Further, even in the case of using a driving circuit consisting of CMOS, in the clocked inverter circuit shown in FIG. 26C for example, there is a period in which the node N between the NMOS transistors N1 and N2 or the node P between the PMOS transistors P1 and P2 is in a floating state in operation. Therefore, as potential of the floating node varies according to the fluctuation of Vcom, there may be caused an operational error, or a decrease in circuit operational margin even operational error is not caused, or a decrease in reliability, same as the case of the dynamic circuit.
In FIG. 23D, in the configuration where the driver 103 is arranged outside the adhesive 108, the above-described problem may be reduced. However, there is caused another problem that the distance from an end of the adhesive 108 to an end of the glass substrate (frame) will become larger. If the frame size of the display area is large, the substrate area increases, which causes to increase the cost, and it is difficult to meet a recent demand of smaller display devices.
Further, in the configuration shown in FIGS. 24A and 24B, a problem of stray capacitance coupling is solved by using the shield layer 80. The resolution shown in FIGS. 24A and 24B is intended for a wiring unit, and is not related to the driving circuit of the liquid crystal display device. Further, by adding a process of producing the shield layer 80, the cost may be increased.
Therefore, if the conventional art described above is applied to a display device performing operation in which potential Vcom of a counter electrode varies temporally, (a) malfunction of driving circuit and a decrease in operational margin and reliability are caused, (b) an increase in the frame length, or (c) high cost may be caused.